They are already reaching 0.4 defects per cm^2 which is below the standard .5 and they still have time to refine the process. Even if TSMCs engineers are better, their yields are still going to be going down as they are going to have to rely on multi patterning EUV to get down to the small geometries. https://www.tomshardware.com/tech-industry/intel-says-defect-density-at-18a-is-healthy-potential-clients-are-lining-up > Cathcing up is twice as expenisve as staying ahead in this biz. Intel made 22 billion last year plus all of the subsidies from the government. One can argue staying behind would be even more expensive for Intel.

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